The present invention relates to semiconductor memories. More specifically, the present invention relates to semiconductor memories employing a page read-out mode and an address transition detecting function.
In semiconductor memory devices an advanced function has been recently proposed. In this function, a read operation progresses in a page mode, in which (m.times.n) data bits are read in, amplified, and then stored in an (m.times.n) sense amplifier. These data bits are then sequentially read out n times through m input/output pins. The unit of a page, for example, can be regarded to as data capacity engaged in memory cells which are connected to a word line and to plural bit lines.
This kind of a read operation using a page mode offers an enhanced read-out speed higher than in any other conventional reading process. It provides multiple data bits per single word line to output terminals throughout multiple succeeding times without delaying for read operation to read the next data bits.
FIG. 1 shows the construction of a conventional semiconductor memory employing a page read operation, where data bits of four times of the number of input/output pins are simultaneously amplified and stored in latch circuits.
As shown FIG. 1, elements of the semiconductor memory used for a basic reading function are involved in connection with themselves, such as memory cell array 10, column gate circuit 12, sense amplifier circuitry 14, pre-decoder 22, row decoder 24, column decoder 26, page decoder 28, address transition detector 30, data output buffer 32 and input/output pads 34. The normal address 16 is applied to address transition detector 30 and predecoder 22; the page address 18 is applied to page decoder 28; and the output enable signal 20 is applied to the data output buffer 32.
FIGS. 2 through 4 show the address transition detector 30, the page decoder 28, and the sense amplifier circuitry 14, respectively.
The read operation in the memory of FIG. 1 can be understood with reference to the timing diagrams of FIGS. 5 and 6, and the circuit diagrams of FIGS. 1 through 4. The timing diagram of FIG. 5 describes a normal read operation, while FIG. 6 shows an abnormal read operation as will be mentioned later.
In FIG. 5, once normal address signals A.sub.2 through A.sub.i are applied to the memory, in the address transition detector 30 of FIG. 2, short pulse signals Sp.sub.i (including their complementary signals .sup.Sp.sbsp.i) and a sum pulse signal SUM are generated through short pulse generators 116 through 120 and a summing amplifier (or summator) 122, respectively. Thereafter, a precharge control pulse PRE is generated from precharge controller 124, based on the sum pulse signal SUM. The short pulse signals are activated at a high level and are merged to form a low sum pulse. When the precharge control pulse PRE is low, it sets corresponding bit lines (e.g., four bit lines for the page read-out) at a predetermined precharge voltage.
When the precharge control pulse PRE rises up to high level from the low level, sense amplifiers 142 through 148 in sense amplifier circuitry 14 of FIG. 4 are conducted to detect data bits loaded on the four bit lines. Output signals from the sense amplifiers 142 to 148 are stored in data latches 150 through 156. Transmission circuits 158 through 164 are respectively controlled by the outputs SS.sub.0 to SS.sub.3 from the page decoder 28 shown in FIG. 3. The output signals from page decoder 28, namely page decoding signals SS.sub.0 through SS.sub.3, are generated through NAND gates 126 to 132 and inverters 134 through 140 in response to the page address signals A.sub.0 and A.sub.1 (including their complementary signals .sup.A.sbsp.0 and .sup.A.sbsp.1). Any one of the page decoding signals does not activate until the page address signals has been operably varied for it. At that time, one of transmission circuits 158 to 164 is enabled because of an activation of a page decoding signal, which responds at least to the page address signals. Thus a data bit held in one of data latches 150 to 156 is transferred to data the output buffer 32 through the corresponding transmission circuit which is enabled by a high leveled page decoding signal. The required output data bit is generated from the data output buffer 32 at time t.sub.1. After this, data bits are generated from t.sub.2 in accordance with subsequent transitions of the page address signals and page decoding signals. As a result, four bits are generated for a single data output buffer corresponding to a single data input/output pin in a normal page read-out operation.
However, an abnormal timing situation, as shown in FIG. 6, results from a difference of propagation timings between the normal address and the page address. The difference of propagation timings may be referred to in general as a skew that is due to malfunctions of control circuits involved in transferring the addresses.
FIG. 6 shows a page address signal that is early and varies a page decoding signal SS.sub.i (i is one of 0 to 3), at time t.sub.S. This turns on the transmission circuit of FIG. 4 and makes the time t.sub.S becomes the point when the precharge control pulse PRE goes to high from low, thus causing sensing operations upon the bit lines to start at that point.
Because of this unwanted activation of the transmission circuit in response to the enabled page decoding signal, an invalid data bit is generated through the data output buffer. Furthermore, referring to FIG. 4, since ground bouncing noise may be induced at an input terminal of the data output buffer 32 when page decoding signal SS.sub.i is high and nodes 166 and 168 remain high, any one of the sensed signals from the sense amplifiers would be deteriorated and affected in a fluctuation thereby. Such abnormal operation arises from the fact that a transmission circuit as shown in FIG. 4 becomes conductive before valid data bits corresponding to one page (e.g., four bits per page) has been generated from sense amplifiers.